Data Dependent Circuit Design: A Case Study

Data dependent circuits are logic circuits specialized to specific input data. They are smaller and faster than the original circuits, although they are not reusable and require circuit generation for each input instance. This study examines data dependent designs for subgraph isomorphism problems, and shows that a simple algorithm is faster than an elaborate algorithm. An algorithm that requires many hardware resources consumes an accordingly longer circuit generation time, which outweighs the performance advantage in execution. 1 Data Dependent Hardware If any input of a logic circuit turns out to be constant, the circuit can be reduced. For example, if any inputs of an AND gate turn out to be zero, the output becomes zero (constant propagation). This reduction can be applied recursively, consequently reducing the logic scale of the circuit. The derived circuit would operate at a higher frequency than the original, because the logic depth and wiring delay would also be reduced by this reduction. Since the consequent circuit becomes dependent on the input data instance, such a circuit is called a data dependent circuit in the following discussion. The obvious drawback of a data dependent approach is that the derived circuit is not reusable. This naturally means that (1) the circuit must be generated for each input instance, and (2) reconfigurable devices such as FPGA must be used. The total execution time T of a data dependent circuit is given by the sum of the circuit generation time Tgen and the execution time Texec. Tgen consists of the time for HDL source code generation, logic synthesis, technology mapping, placement, routing, and FPGA configuration. Tgen depends on the logic scale, since a larger circuit usually requires accordingly larger generation time. Texec is the product of cycle count and cycle time. Here, the cycle count depends on the algorithm, and the cycle time depends on the implementation. Fast algorithms can make Texec smaller, but they often require more hardware resources and make Tgen larger. The total execution time T is thus not so obvious without empirical studies.